1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same.
2. Description of the Related Art
In a planar power MOS transistor in the art, a current path is identical to a breakdown voltage sustainable path. Therefore, a larger thickness of an epitaxial layer for achievement of a higher breakdown voltage results in an increased on-resistance. In contrast, a smaller thickness of the epitaxial layer for achievement of a lower on-resistance results in a reduced breakdown voltage. The presence of such the contradictory relation makes it difficult to satisfy both characteristics at the same time.
A recently proposed power MOS transistor called Super Junction structure has a current path separated from a breakdown voltage sustainable path. In this power MOS transistor, an n-type semiconductor pillar layer serving as the current path and a p-type semiconductor pillar layer serving as a current partition region are alternately arranged in the lateral direction. An n-type source region and a gate electrode are formed in and above a p-type semiconductor base layer formed on the upper surface of the p-type semiconductor pillar layer. (For example, see JP-A 2002-170955, pages 5-8, FIG. 3, and JP-A 2001-119022, pages 4-5, FIG. 1).
In this structure, the on-resistance depends on a carrier concentration in the n-type semiconductor pillar layer because a drain current flows in the n-type semiconductor pillar layer. On the other hand, the breakdown voltage depends on carrier concentrations and widths of the n-type and p-type semiconductor pillar layers because depletion layers extend in the lateral direction.
In the MOS power transistor disclosed in JP-A 2002-170955, an n-type silicon (Si) substrate is provided to form a thick n-type epitaxial Si layer thereon, and deep trenches are formed in the Si layer down to a depth reaching the Si substrate. Then, boron (B) as a p-type impurity and arsenic (As) as an n-type impurity having a smaller diffusion coefficient than that of B are implanted at the same time into sides of the trenches. A process of heating is then applied to diffuse B and As at the same time into a region sandwiched between the trenches. As a result, the region sandwiched between the trenches is provided with a p-type semiconductor pillar layer formed at the center and an n-type semiconductor pillar layer formed in the outer rim at the same time.
In the MOS power transistor disclosed in JP-A 2001-119022, the step of forming a thin n-type epitaxial Si layer on an n-type Si substrate and the step of implanting B as a p-type impurity into a certain location in the n-type epitaxial Si layer are employed. These steps are repeated alternately to form a thick semiconductor layer, followed by heating to diffuse B in the semiconductor layer. As a result, B-diffused regions are connected vertically with each other to form a p-type semiconductor pillar layer and non-B-diffused regions in the semiconductor layer are employed as an n-type semiconductor pillar layer.
In the MOS power transistor disclosed in JP-A 2002-170955 or JP-A 2001-119022, the upper and lower regions in the semiconductor pillar layer are determined equal in carrier concentration to achieve a lower on-resistance and a higher breakdown voltage at the same time.
If the upper and lower regions in the semiconductor pillar layer are equal in carrier concentration, however, the semiconductor pillar layer is given a narrow charge unbalance margin. Accordingly, if the carrier concentration and width of the semiconductor pillar layer cannot be obtained as designed, a problem may arise because the breakdown voltage of the power MOS transistor is reduced.
Particularly, when the width of the semiconductor pillar layer is made narrower and the carrier concentration is controlled higher to reduce the on-resistance per unit area in the power MOS transistor, the breakdown voltage of the power MOS transistor is reduced remarkably.
The charge unbalance margin herein means how much design tolerance on the carrier concentration and width of the semiconductor pillar layer may be allowed without reducing the breakdown voltage. Qn is herein defined as a pillar charge amount represented by a product of the carrier concentration by the width of the n-type semiconductor pillar layer, while Qp is defined as a pillar charge amount represented by a product of the carrier concentration by the width of the p-type semiconductor pillar layer. Then, the design tolerance is defined in relation to a deflection (Qn−Qp)/Qn from an ideal state in which Qn is equal to Qp so that complete depletion can be achieved.
In consideration of various variations at the process steps of manufacturing the power MOS transistor, the charge unbalance margin is desirably±15% or more.